1. Field of the Invention
The present invention relates to a semiconductor device having an interconnection connected to a conductive layer present above a semiconductor substrate as well as to a manufacturing method thereof.
2. Description of the Background Art
Conventionally, a method of manufacturing a semiconductor device including the step of forming a hole penetrating a second interlayer insulating film covering a conductive layer formed on a first interlayer insulating film and reaching the conductive layer has been employed. In the method of manufacturing a semiconductor device, if a position at which the hole is formed is displaced from a position of the conductive layer, the hole reaches the first interlayer insulating film under the conductive layer. Such penetration caused by misalignment of the hole is more likely in a recent semiconductor device that has been reduced in size.
As a technique to prevent the hole from penetrating as far as the first insulating film under the conductive layer due to misalignment of the hole as described above, Japanese Patent Laying-Open No. 05-299515 discloses a technique to provide an etching stopper film solely on a sidewall of the conductive layer. In addition, Japanese Patent Laying-Open No. 2000-294631 discloses a technique to provide double etching stopper film in a damascene structure. Moreover, Japanese Patent Laying-Open No. 09-007970 discloses a technique to provide an etching stopper film only on a lower side of the conductive layer.
None of the techniques described above, however, can completely solve the problem of the hole reaching the first interlayer insulating film.